A multistep analog-to-digital converter (ADC) is an electronic circuit in which two or more successive conversion cycles are used to compare an input voltage against successively finer ranges of reference voltages in order to produce a high resolution digital representation of the input voltage.
A key element in both flash and multistep ADCs is a resistor ladder that is used to generate a stepped set of reference voltages. Typically, a reference voltage Vref is divided by the resistor ladder by 2.sup.N resistors into equal sized voltage steps. The input voltage is then compared with each voltage step, or at least a subset of the voltage steps, in order to determine the magnitude of the input voltage being converted into digital form. The architecture and operation of a multistep ADC will be discussed in much more detail below.
The key point here is that it is very important for all of the 2.sup.N resistors in the resistor ladder to be precisely equal in resistance. Especially in multistep ADCs, resistance variations of even 0.025 percent can compromise the linearity and accuracy of a 12-bit ADC. However, the standard semiconductor circuit manufacturing techniques used to manufacture ADCs often produce resistors with resistance mismatches of as much as 0.2 percent. Trimming of resistors using lasers, in order to make resistors of precise resistance, is well known in the art but is not financially feasible for high volume, medium-cost, ADCs. Another technique known in the art to correct for ADC non-linearities is to store a table in memory of correction values, and to then use computer software to adjust each digital value output by the ADC with a corresponding correction value read from the stored table. However this technique is not suitable in many commercial applications, either because a microprocessor or microcontroller is not used in the application, or because the relevant system lacks sufficient memory storage or microprocessor computation cycles to use this technique, or because the technique is insufficiently accurate.
It is the primary object of the present invention to provide an improved ADC circuit that includes an embedded correction memory as well as an associated internal voltage adjustment circuit for "trimming" the effective resistance of the resistors in the ADC's resistor ladder. Another object of the present invention is to increase the resolution of the digital conversion value generated from 10 bits to 12 bits without having to use either an additional resistor ladder or additional comparator circuits.